1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device. In particular, it relates to a method of manufacturing a semiconductor device comprising damascene interconnections.
2. Description of the Related Art
Recently, copper having a lower specific resistance has been often used as a material for an interconnection in a semiconductor device. Since it is difficult to perform reactive ion etching on copper, the damascene process is usually employed for forming the interconnection when using copper as the interconnect material. Known damascene processes include a single damascene process in which an interconnection layer and a via hole are stepwise formed and a dual damascene process in which an interconnection layer and a via hole are simultaneously formed. Among these, a dual damascene process, disclosed in JP-A No. 2002-203898 for example, is advantageous in the light of reduction in the number of steps because the via hole and the interconnection trench are simultaneously buried. The via hole may be made of the same type of copper as that for the interconnection to reduce a resistance of the via hole.
Forming an interconnection structure using a dual damascene process can be conducted by a via-first or trench-first process. In a via-first process, a via hole is first formed and an interconnection trench is then formed such that the trench is superposed over the via hole pattern. On the other hand, in a trench-first process, an interconnection trench is first formed and a via hole is then formed such that the via hole is superposed over the trench. The former is advantageous in the light of ensuring good contact performance of the via hole. Now referring to FIGS. 1A to 1D and 2A to 2D, conventional via-first steps of the dual damascene process will be described below.
FIG. 1A shows the step in which a first interconnection 103, diffusion barrier film 105 and a second insulating film 107 are sequentially formed on a substrate (not shown in the drawings). After depositing a first insulating film 101 on the substrate, an interconnection trench is formed by dry etching and then a barrier metal film (not shown in the drawings) and a copper film are formed in sequence such that the trench is filled with them. Then, extraneous barrier metal and copper films formed outside of the interconnection trench are removed by CMP (Chemical Mechanical Polishing), to form the first interconnection 103. Next, on the first interconnection 103 is formed the diffusion barrier film 105. The diffusion barrier film 105 is formed for preventing copper from diffusing into the insulating film and is also used as an etching stopper film during forming a via hole 111. Then, on the diffusion barrier film 105 is formed the second insulating film 107.
The second insulating film 107 is an interlayer insulating film having a lower dielectric constant. Thus, the structure of FIG. 1A is provided.
Then, as shown in FIG. 1B, on the second insulating film 107 are sequentially formed an anti-reflection film (not shown in the drawings) and a resist film 109, and a resist pattern for the via hole 111 is formed by lithography. Then, the via hole 111 is formed by dry etching. During the process, etching is stopped on the diffusion barrier film 105, utilizing a difference in an etching rate between the second insulating film 107 and the diffusion barrier film 105 for preventing copper contamination due to exposure of the first interconnection 103, ashing after etching and damage to the copper during a washing procedure. After etching, the resist film 109 and the anti-reflection film are removed by ashing.
Then, as shown in FIG. 1C, on the second insulating film 107 are sequentially formed an anti-reflection film (not shown in the drawings) and a resist film 115, and then a resist pattern for the interconnection trench 117 is formed as described above. Then, the interconnection trench 117 is formed by dry etching. During the process, the bottom of the via hole 111 is not etched because the anti-reflection film or the resist film 115 is buried.
Then, as shown in FIG. 1D, the resist film 115 and the anti-reflection film are removed by ashing. Next, as shown in FIG. 2A, the diffusion barrier film 105 in the bottom of the via hole 111 is removed by dry etching to expose the first interconnection 103.
Then, as shown in FIG. 2B, a barrier metal film 119 and a copper film (not shown in the drawings) to be a seed layer for electroplating are sequentially formed by sputtering over the whole surface of the second insulating film 107 including the via hole 111 and the interconnection trench 117. Subsequently, a copper film 121 is buried in the via hole 111 and the interconnection trench 117 by electroplating.
Then, as shown in FIGS. 2C and 2D, the extraneous copper film 121 and barrier metal film 119 are removed by CMP.
As described above, there are formed the copper film 121, i. e., the second interconnection in the interconnection trench 117, and the via hole connecting the first interconnection 103 with the second interconnection.